Simplify your tests with the removal of boilerplate.
Reuse existing functionality easily dramatically accelerating test development.
Increase your defect removal efficency with early integration of verification into your development flow.
Bulit in regression manager with test case auto-discovery.
VHDL and Verilog support with no test changes.
Compaitible with all major commercial simulators.
Open source and hosted on github.
Exploit the wealth of Python knowledge already freely available. Image handling, networking, math libraries are easily integrated to enable complex functionality with minimal test code.