Define your register maps easily using Python, IP-XACT, JSON or YAML.
Access your device via PCIe, Ethernet, I2C from an elegant C++ or Python API.
Debug your registers with live interactive datasheets.
Integration with Altera Qsys for component auto-discovery.
Self-describing components with automatic register map versioning.
Dynamically load the correct register map version at run-time.
GMP bignum support. Elegant C++ class library. SystemVerilog register mappers for AXI-4 Lite, Avalon-MM and Wishbone. Support for auto-clearing registers, paged memory regions, safe atomic accesses and much more.
A single definition for software, hardware and documentation. Automated register validation and hassle free management of register versioning