By abstracting away the interface xactly allows you to focus on functionality.
Define
Define your register maps easily using Python, IP-XACT, JSON or YAML.
Access
Access your device via PCIe, Ethernet, I2C from an elegant C++ or Python API.
Debug
Debug your registers with live interactive datasheets.
Our unique extensible architecture allows unprecedented flexibility
Integration with Altera Qsys for component auto-discovery.
Self-describing components with automatic register map versioning.
Dynamically load the correct register map version at run-time.
An entire toolbox
GMP bignum support. Elegant C++ class library. SystemVerilog register mappers for AXI-4 Lite, Avalon-MM and Wishbone. Support for auto-clearing registers, paged memory regions, safe atomic accesses and much more.
Focus on functionality
Abstract away register bus width. Re-use IP in multiple designs. Add new registers in seconds.
Remove manual steps
A single definition for software, hardware and documentation. Automated register validation and hassle free management of register versioning
Document
Generate readable documentation. Print human-readable decodes of entire register space. Debug console access with tab-completion, in-line documentation and more.