Verification Futures 2015

Fri 06 February 2015

Posted by Chris Higgs   

There was a good turnout at Verification Futures in Reading yesterday. It was great to meet with other engineers and vendors, swap stories and catch up.

It was also interesting to hear about the verification challenges faced by larger organisations and pitches from some of the vendors for their latest and greatest solutions. It was clear that there's an undercurrent of frustration with the tools - a great comment from Wez Davey explaining the understandable reaction to a 3 man month budget for fighting tool bugs in a project! It sounds ridiculous, but these are the realities of our environment.

There were also many remarks about the UVM, almost "Universally" negative. Execution is too slow (and getting slower), it's too complex, too difficult to use outside of simulation and takes too long to learn. Hardly glowing praise of the industry's favourite methodology!

Python is definitely gaining traction in the EDA world. For example Wez Davey revealed that Python is used extensively in DisplayLink for writing portable tests that can run against simulation, FPGA prototyping platforms or the fabbed ASIC. Interestingly he commented that this Python framework originated from the software / firmware teams and had been adopted as an integral part of their ASIC development flow.

We saw several other cases where adoption of improved development flows have spilled over from the software teams. Alan Fitch explained that the software group had already implemented Jenkins for Continuous Integration, helping the FPGA team avoid the common pitfall of inventing their own mechanism using TCL.

Agile was mentioned in passing in several of the presentations. We gave a brief presentation about applying agile techniques to FPGA development and based on the discussions afterwards this is a popular topic. Here are the slides: